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ECET-230 – Digital Circuits and Systems Homework Assignment #4 Name ____________________________ 1. Sketch the Q output for the waveforms shown below applied to an active-LOW S-R latch. Assume that Q starts LOW.

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ECET-230 – Digital Circuits and Systems
Homework Assignment #4

Name ____________________________

  1. Sketch the Q output for the waveforms shown below applied to an active-LOW S-R latch. Assume that Q starts LOW.
  • Sketch the Q output for the waveforms shown. Assume that Q starts LOW.
  • Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
  • Sketch the Q output for the circuit shown below. Assume that Q starts LOW.




  • Sketch the Q output for the circuit shown below. Assume that Q starts LOW.



  • Sketch the Q output for the circuit shown below. Assume that Q starts LOW.





  • Sketch the Q output for the circuit shown below. Assume that Q starts LOW.
CLK   P   R   J   K   Q  

Sketch the Q output for the circuit shown below. Assume that Q starts LOW.

  • Using Quartus II, or an equivalent VHDL entry program, model the D flip-flop shown below. Attach the simulation file.
  1. Using Quartus II, or an equivalent VHDL entry program, model the J-K flip-flop shown below. Attach the simulation file.
 
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