Write a VHDL module to implement an 8-bit serial-in, serial-out right-left shift register with inputs RSI, LSI, En, R, and CLK. RSO and LSO are the serial outputs, so they should be the rightmost and leftmost bits of the register. However, the values of the other flip-flops inside the register should not appear on the outputs. When En = 1, at the rising edge of the clock, the register shifts right if R = 1 or left if R = 0. RSI should be the shift-in input if R = 1, and LSI should be the shift-in input if R = 0. When En = 0, the register holds its state. There should also be an asynchronous active- low clear input ClrN. Use the following test cases: – reset – set LSI = 0; RSI = 1 – set En = 0 for 2 clock cycles = 1 for the rest of the test – Shift Right 9x – Shift Left 9x Create a state diagram, a block diagram, and the vhdl code.
Write a VHDL module to implement an 8-bit serial-in, serial-out right-left
shift register with inputs RSI, LSI, En, R, and CLK. RSO and LSO are the serial outputs, so they should be the rightmost and leftmost bits of the register. However, the values of the other flip-flops inside the register should not appear on the outputs. When En = 1, at the rising edge of the clock, the register shifts right if R = 1 or left if R = 0. RSI should be the shift-in input if R = 1, and LSI should be the shift-in input if R = 0. When En = 0, the register holds its state. There should also be an asynchronous active- low clear input ClrN.
Use the following test cases:
– reset
– set LSI = 0; RSI = 1
– set En = 0 for 2 clock cycles
= 1 for the rest of the test
– Shift Right 9x
– Shift Left 9x
Create a state diagram, a block diagram, and the vhdl code.
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